VLSI Implementation for Low Noise Power Efficiency Cellular Communication Systems

VLSI Implementation for Low Noise Power Efficiency Cellular Communication Systems

A low power model for Code Division Multiple Access (CDMA) based cellular communication system is developed. The dynamic power is minimized by reducing the frequency of the Phase Lock Loop (PLL) after lock is established. The paper addresses the feasibility of lowering the clock frequency of the processing unit that models the PLL is addressed and modulator/demodulator functions of the system w...

Efficiency of Adiabatic Logic for Low-Power, Low-Noise VLSI

ln this paper, the efficiency of a fully adiabatic logic circuit is compared with its combinational and pipelined static CMOS counterparts. The performance of each circuit is studied in terms of the maximum frequency of operation, the minimum voltage of operation, the circuit energy consumption, and the switching noise generated by the circuit. An 8-bit carry look-ahead adder is designed using ...

Low-Power Equalizer VLSI Implementation for xDSL

A Low-Power VLSI Implementation for Efficient Removal of Impulse Noise using CLA

The impulse noise is caused by sharp, sudden disturbances in the image signal. Its appearance is randomly scattered white or black (or both) pixels over the image. In this paper, an efficient VLSI implementation for removing impulse noise using CLA is presented. Our result preserves the edge features and obtains excellent performances in terms of quantitative evaluation and visual quality The d...

Low power DCT implementation approach for VLSI DSP processors

This paper presents an algorithm for the low power implementation of the Discrete Cosine Transform on Single multiplier CMOS DSPs. The algorithm reduces power by a combination of using shift operations, where possible, and manipulating bit-correlation between successive cosine coefficients applied to the input of the multiplier section such that the effective switched capacitance is reduced. Th...